1. Field of the Invention
The present invention relates to a CMOS transistor to be formed on an SOI substrate and a method for forming the SOI substrate for the CMOS transistor.
2. Description of Related Art
For manufacturing an SOI substrate in a low temperature process, a wafer bonding method using a boron phosphor silicate glass (BPSG) has been proposed. A structure of the SOI substrate formed by this manufacturing method is described below.
As shown in FIG. 1, a boron phosphor silicate glass (BPSG) layer 2 is located on the bonding surface of the substrate 1. In addition, a polycrystalline silicon layer 11 and a silicon oxide layer 12 for embedding are located on a side to be bonded onto the BPSG layer 2. A plurality of silicon regions 13 and 14 are located on the silicon oxide layer 12.
Devices such as MOS transistors and nodes are formed on the silicon regions 13, 14. FIG. 1 shows a CMOS transistor formed on the substrate.
nMOS transistors 13, 15 are formed on the silicon region 13 while pMOS transistors 14, 16 are formed on the silicon region 14.
In addition, an interlayer insulation film 17 is formed to cover the nMOS and pMOS transistors 15, 16.
However, the polycrystalline silicon layer below the CMOS transistor remains electrically floating. Therefore, the potential of the polycrystalline silicon layer is unstable, and affects the channel and node potentials of the nMOS and pMOS transistors through the silicon oxide layer. This is a cause of faulty operation or circuit malfunction.
In order to avoid the above problem, a structure as shown in FIG. 2 has been proposed.
Specifically, as described in the prior art, the nMOS transistor 15 is formed on the silicon region 13 and the MOS transistor 16 is formed on the silicon region 14.
A contact hole 21 is formed, through the silicon oxide layer 12 and the interlayer insulation film 17, to the polycrystalline silicon layer 11. Moreover, an electrode 22 is connected with the polycrystalline silicon layer 11 through the contact hole 21, for fixing the potential at a specified value.
However, in a CMOS transistor circuit comprising the nMOS transistor 15 and the pMOS transistor 16 as described above, the back channel of the pMOS transistor 16 is formed as an enhancement type in a case that, for example, the polycrystalline silicon layer 11 is regarded as a gate and the potential of the polycrystalline silicon layer 11 is fixed so that the back channel of the nMOS transistor 15 is formed as a depression type. Therefore, a leak current increases. The thinner a film of the silicon oxide layer 12 becomes, the more this phenomenon will be intensified.
A method for doping impurities in the polycrystalline silicon layer 11 is available as a method for reducing the leak current. In this method, however, grinding for smoothing the polycrystalline silicon layer 11 is difficult because impurities should be doped in the polycrystalline silicon layer 11 before grinding for smoothing the polycrystalline silicon layer 11. In other words, it is difficult to mirror-finish the surface of the polycrystalline silicon layer 11 in which impurities are doped in high concentrations.